1. Field of the Invention
The present invention relates to a non-volatile memory system, and more particularly, to a non-volatile memory system which may include a plurality of memory cell arrays having different read stand-by times, and to method of reading data in a non-volatile memory system.
2. Description of the Related Art
Non-volatile memory devices, such as flash memory, retain data in the absence of supplied power. Each memory cell of flash memory is composed of a cell transistor. The cell transistor includes a control gate, a floating gate, a source, and a drain, and is programmed or erased by utilizing a mechanism known as Fowler-Nordheim (F-N) tunneling.
An erasing operation of the cell transistor is performed by applying a low voltage (e.g., ground) to the control gate and a relatively high voltage (higher than a source voltage) to a semiconductor substrate or a bulk. Under this erase bias condition, a strong electric field is formed between the floating gate and the bulk due to the large voltage difference therebetween, and thus F-N tunneling is induced in which electrons of the floating gate are emitted to the bulk. As a result, a threshold voltage of the erased cell transistor is moved in a negative direction.
A programming operation of the cell transistor is performed by applying a high voltage (higher than a source voltage) to the control gate and a low voltage (e.g., ground) to the drain and the bulk. Under this programming bias condition, F-N tunneling is induced such that electrons are injected into the floating gate of the cell transistor. As a result, the threshold voltage of the programmed cell transistor is moved in a positive direction.
FIG. 1 is a diagram for describing the structure and threshold voltage distribution of a single-bit memory cell included in a non-volatile memory device.
Referring to FIG. 1, a memory cell includes a control gate CG and a floating gate FG. As shown in the right side of FIG.1, a programming state PROGRAM is characterized by electrons filling the floating gate FG of the memory cell. As a result, the threshold voltage (Vth) distribution is greater than 0V. In contrast, referring to the left side of FIG. 1, an erasing state ERASE is characterized by an absence of electrons in the floating gate FG. In this state, the threshold voltage distribution is less than 0V. The two different threshold voltage distributions allows for storage of a single bit data (1 or 0) in each cell. In FIG. 1 the Y-axis (NO. OF CELL) denotes a number of cells of each of the ERASE and PROGRAM threshold volta e distributions.
In contrast, multi-level cell (MCL) flash memory is characterized by storing two or more bits per cell. For example, in the case of two-bit cells, the threshold voltage of each cell can fall within one of four different threshold distributions, which respectively denote two-bit data 11, 01, 10, and 00. In this case, 11 is typically designated as an erased state, and 01, 10, and 00 are program states.
FIG. 2 is a diagram for describing the structure and threshold distributions of a multi-level cell included in a non-volatile memory device.
Referring to FIG. 2, each memory cell includes a control gate CG, a floating gate FG, N-doped source and drain N+, and P-doped substrate P+SUBSTRATE. An erased state (1st state) has the lowest threshold distribution and is characterized by an absence of electrons in the floating gate FG. The three program states (2nd, 3rd and 4th states) are characterized by progressively higher numbers of electrons in the floating gate FG, which results in progressively higher threshold voltage distributions.
A non-volatile memory system may conceivably include both single-level cells (SLCs) and multi-level cells (MLCs). However, implementation of such a system is complicated by the fact that different read times are associated with SLC and MLC systems. That is, the time required for an MLC to receive a read instruction and to read data is at least twice as long as the time required for an SLC to receive a read instruction and to read data.